This invention relates to a line deflection circuit with a dynamic S-correction circuit, a dynamic S-correction circuit, and a display apparatus comprising such a dynamic S-correction circuit.
Flatter and shallower picture tubes, (election tubes, cathode ray tubes) are showing a strong increase of geometric errors like especially the so-called moustache effect and inner-pin. The moustache effect is a geometric error where the cross-hatch width at the start and end of the picture is much smaller compared to the middle. Compensating these increased higher order errors is difficult and almost impossible to realize with conventional circuits. Methods like, high frequent modulating the deflection current, or inserting e.g. controlled and regulated saturable inductors in series with the yoke are complex, expensive and dissipative.
The moustache effect as well as the inner pin distortion can be overcome by adapting the value of the S-capacitor during a certain interval of the scan time. In this way an improved S-shaped deflection current can be realized, and the above mentioned higher order errors can be compensated for any picture tube.
Most picture tubes suffer from the so-called xe2x80x9cMoustache effectxe2x80x9d. This is a geometric error visible as a compression of the picture displayed on the screen of the picture tube at the begin and end of the screen compared to the middle of the screen. Adaptation of the value of the S-capacitor during a certain time interval of the scanning interval is a known method to compensate this error. The inner-pin distortion can be compensated at the same time by modulating this time interval as a function of a frame frequent correction waveform.
U.S. Pat. No. 5,949,201 discloses a deflection circuit which has a first S-correction capacitor in series with a line deflection coil. A second S-correction capacitor is connected in parallel with the first S-correction capacitor via a MOS-FET during the left-hand and the right-hand ends of the screen. Sawtooth generator circuits and comparator circuits control the on-periods of the MOS-FET to vary in the vertical direction such that an amount of intermediate pin distortion (usually referred to as inner-pin distortion) is sufficiently corrected. A high voltage capacitive divider is required to supply an input signal to the sawtooth generators. Consequently, this prior art dynamic S-correction circuit is quite complex. Further, the capacitive divider is expensive.
It is, inter alia, an object of the invention to provide a line deflection circuit with a dynamic S-correction circuit which corrects the inner pin distortion and which is less complex.
To this end, a first aspect of the invention provides a deflection circuit with a dynamic S-correction circuit including a control circuit operative with a voltage comprising a DC and an AC component. A second aspect of the invention provides a dynamic S-correction circuit including the aforesaid control circuit. Advantageous embodiments are defined in the dependent claims. A third aspect of the invention provides a display apparatus including the aforesaid dynamic S-correction circuit.
The line deflection circuit in accordance with the invention comprises a first S-correction capacitor arranged in series with the line deflection coil. A substantially sawtooth shaped deflection current through the line deflection coil causes a substantially parabola shaped voltage across the first S-correction capacitor. This substantially parabola shaped voltage comprises a DC-component and an AC-component. A dynamic S-correction circuit comprises an arrangement of a switch and a second S-correction capacitor. In one of the states of the switch, the total S-capacitance is determined by both a value of the first and the second S-capacitor. In the other state of the switch, the total S-capacitance is determined by the value of the first S-capacitor only. A comparator controls an instant of switching of the switch by comparing the substantially parabola-shaped voltage across the first S-correction capacitor with a reference level.
As in a line deflection circuit the amplitude of the line deflection current will vary in the vertical direction in accordance with the East-West modulation to correct the pin distortion, the substantially parabola-shaped voltage varies in the vertical direction. Consequently, the comparator, which compares this varying substantially parabola-shaped voltage with the reference level, automatically adapts the switching instant of the switch to correct the inner pin distortion.
EP-A-0 823 812 discloses a horizontal S-shape correction circuit. The turn-off period of the FET is adjusted by changing the output pulse width of the driver circuit of the FET according to the horizontal deflection frequency, to adjust the total capacitance value of the S-shape correcting capacitor group in one horizontal deflection period, that is, to execute an optimum S-shape distortion correction according to each horizontal deflection frequency. The timing at which the electronic switch element is turned off in a first half of the horizontal scanning period is continuously and variably controlled on the basis of an external control signal (Vg). The auxiliary S-shape correcting capacitor of the S-shape correcting capacitor group is controllably turned on or off by the electronic switch element, to execute an optimum S-shape distortion correction.
FIG. 14 of this prior art shows a detecting circuit (referred to as 208) generating a DC-level (referred to as Epb) indicating an amplitude of the voltage across the S-correction capacitor (referred as 7). A comparator (referred to as 209) compares this DC-level with a reference level. In this way, an optimal S-correction is obtained at different horizontal deflection frequencies. The circuit of the prior art does not compare a combination of the DC- and the AC-component of the voltage across the S-correction capacitor with the reference. This prior art circuit does not correct the inner-pin distortion, but the S-shape (thus the pin distortion) as a modulation of the S-shape is not disclosed.
The practical implementation of the circuits improving the horizontal linearity and the inner-pin is different and much simpler than the methods published in the prior art cited above. The required modulation of the On and Off periods or the xcex4-cycle as a function of the frame to compensate the inner pin distortion are obtained by using the parabolic waveform across the S-capacitors. This parabolic waveform is modulated by the East-West information (in a usual TV application) or B+modulation (the modulation of the power supply voltage of the line deflection circuit in a usual monitor application). So, the xcex4-cycle will be modulated by the same low frequent East-West information and to produce the correct inner-pin correction.
This method gives the desired corrections, independent of the scan frequency over a relatively large range.
An embodiment of the invention, in which the dynamic S-correction circuit has only two terminals connected across the first S-correction capacitor, is based on the insight that the voltage across the first (also referred to as main) S-capacitor contains all of the information required to determine the ON and OFF instants of the switch. This has the practical advantage that the drive circuit is fully self-supporting. In other words, the drive circuit receives the parabolic waveform across the main S-capacitor to generate, without other interfaces or power supplies, the ON and OFF times (or xcex4 cycle) for the switch so as to compensate the horizontal linearity or moustache effect, and the required modulation of this xcex4-cycle as a function of the frame position to compensate the inner-pin distortion. Consequently, this manner of geometry correction can, for TV applications, be assembled on the yoke and optimized as a unit together with the picture tube.
Both the embodiment as defined in claim 3, and the embodiment as defined in claim 4 have the advantage that the amount of the AC component fed to the comparator is selectable for influencing the switching instants of the switch to obtain an optimal performance for the inner-pin distortion correction.